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We characterized resistance drift in phase change memory devices in the 80 K to 300 K temperature range by performing measurements on 20 nm thick, ∼70–100 nm wide lateral Ge₂Sb₂Te₅(GST) line cells. The cells were amorphized using 1.5–2.5 V pulses with ∼50–100 ns duration leading to ∼0.4–1.1 mA peak reset currents resulting in amorphized lengths between ∼50 and 700 nm. Resistance drift coefficients in the amorphized cells are calculated using constant voltage measurements starting as fast as within a second after amorphization and for 1 h duration. Drift coefficients range between ∼0.02 and 0.1 with significant device-to-device variability and variations during the measurement period. At lower temperatures (higher resistance states) some devices show a complex dynamic behavior, with the resistance repeatedly increasing and decreasing significantly over periods in the order of seconds. These results point to charge trapping and de-trapping events as the cause of resistance drift.

 

Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing ( Vside ). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage ( Vt ) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm × 78 nm (width × length) device shows SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and Vt increasing from 0.42 to 0.61 V as the temperature is reduced from 400 to 100 K. Vt can be adjusted from ∼ 0.3 to ∼ 1.1 V with ∼ 0.3 V/V sensitivity by depletion or accumulation of the body of the device using Vside . This high level of tunability allows electronic control of Vt and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents ( < 10 −13 A). 

We calculate critical electronic conduction parameters of the amorphous phase of Ge 2 Sb 2 Te 5 (GST), a common material used in phase change memory. We estimate the room temperature bandgap of metastable amorphous GST to be E g (300K) = 1.84 eV based on a temperature dependent energy band model. We estimate the free carrier concentration at the melting temperature utilizing the latent heat of fusion to be 1.47 x 10 22 cm -3 . Using the thin film melt resistivity, we calculate the carrier mobility at melting point as 0.187 cm 2 /V-s. Assuming that metastable amorphous GST is a supercooled liquid with bipolar conduction, we compute the total carrier concentration as a function of temperature and estimate the room temperature free carrier concentration as p(300K) ≈ n(300K) = 1.69×10 17 cm -3 . Free electrons and holes are expected to recombine over time and the stable (drifted) amorphous GST is estimated to have p-type conduction with p(300K) ≈ 6×10 16 cm -3 . 

Phase change memory (PCM) is a high speed, high endurance, high density non-volatile memory technology that utilizes chalcogenide materials such as Ge 2 Sb 2 Te 5 (GST) that can be electrically cycled between highly resistive amorphous and low resistance crystalline phases. The resistance of the amorphous phase of PCM cells increase (drift) in time following a power law [1] , which increases the memory window in time but limits in the implementation of multi-bit-per-cell PCM. There has been a number of theories explaining the origin of drift [1] - [4] , mostly attributing it to structural relaxation, a thermally activated rearrangement of atoms in the amorphous structure [2] . Most of the studies on resistance drift are based on experiments at or above room temperature, where multiple processes may be occurring simultaneously. In this work, we melt-quenched amorphized GST line cells with widths ~120-140 nm, lengths ~390-500 nm, and thickness ~50nm ( Fig. 1 ) and monitored the current-voltage (I-V) characteristics using a parameter analyzer ( Fig. 2 ) in 85 K to 350 K range. We extracted the drift co-efficient from the slope of the resistance vs. time plots (using low-voltage measurements) and observed resistance drift in the 125 K -300 K temperature range ( Fig. 3 ). We found an approximately linear increase in drift coefficient as a function of temperature from ~ 0.07 at 125 K to ~ 0.11 at 200 K and approximately constant drift coefficients in the 200 K to 300 K range ( Fig. 3 inset). These results suggest that structural relaxations alone cannot account for resistance drift, additional mechanisms are contributing to this phenomenon [5] , [6] .